In recent years devices have been fabricated in a thin silicon layer on a silicon substrate. The technique for building the silicon layer on the insulating substrate is referred to as the silicon on insulator (SOI) technique. A complementary metal oxide semiconductor (CMOS) device in the silicon on insulator has good device characteristics, for example, high speed and low power. In IEDM Tech. Dig., on page 129 on 1996, S. Maeda et al. reported that a deep sub-micron SOI circuit is manufactured by using field shield isolation technology. The paper is entitled "Suppression of Delay Time Instability on Frequency using Field Shield Isolation Technology for Deep Sub-Micron SOI Circuits". The authors were successful in suppressing delay time instability depending on frequency using field shielding isolation technology for deep sub-micron SOI circuits and preventing the instability over wide input frequency range. The method of the paper offered a stable circuit operation compatible with bulk circuits by using field shielding isolation technology while keeping SOI benefits. In this paper, separation by implanted oxygen (SIMOX) was used to form a thin silicon layer on an insulator (SOI) and a MOS device was constructed on the SOI without any area penalties in gate array. The gate layer of the MOS device has a thickness about 70 angstroms, a SOI layer of the device has a thickness about 1000 angstroms and a buried oxide layer has a thickness about 4000 angstroms in this paper.
The SOI CMOS transistors have a better latch-up immunity, a better short channel behavior, a process-simplification advantage and a higher device speed than the bulk CMOS transistors. The SOI CMOS transistors are usually fabricated for radio-frequency application. Babcock demonstrated a TFSOI BiCMOS device in IEDM Tech. Dig., page 133, 1996. The title of the paper is "Low-Frequency Noise Dependence of TFSOI BiCMOS for Low Power RF Mixed-Mode Application". Babcock proposed a TFSOI BiCMOS device designed for low power RF mixed-mode application. Separation-by-implantation-of-oxygen (SIMOX) material with 0.1 micrometers silicon thickness and a 0.4 micrometer buried oxide are used for the process. The technology is based on a fully manufacturable TFSOI 0.5 micrometers LDD CMOS and lateral bipolar process which consists of poly-buffered-LOCOS isolation, 105 angstroms gate oxide, self-aligned silicided contacts, and 2-layer metallization.
However, the electrostatic shielding discharge (ESD) voltage of SOI CMOS output buffers is smaller than the ESD voltage of bulk NMOS buffers. Chan tried to realize the ESD voltage of SOI CMOS output buffers and bulk NMOS buffers, as reference to IEEE Trans. Electron Devices, vol. ED-42, page 1816, 1995. The title of the paper is "ESD Reliability and Protection Schemes in SOI CMOS Output Buffers". Chan pointed to the result that ESD voltage sustained by the bulk SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. The authors tried to fabricate ESD protection circuit on the SOI substrate in order to enhance ESD reliability. The conclusion of the paper was that most of the method developed in bulk technology to improve ESD performance is not effective as well in SOI circuits. Chan proposed an alternative process of the through oxide ESD protection scheme. The cross sectional view of SOI MOS and bulk MOS was demonstrated in the FIG. 1 according to the paper as a finger structure to achieve a more uniform current density. The silicon film thickness and the buried oxide thickness of the devices as were mentioned above are 1630 and 1134 angstroms, respectively.